Many systems such as parallel processor systems, artificial intelligence systems, or multimedia systems, typically include a plurality of cooperating sub-systems for processing data. One decisive problem for the efficient practical realization of these systems is the storage of data to be processed, as well as their data processing programs. The most powerful systems would be realizable if a memory is available to which the sub-systems can gain access chronologically parallel and with a high bandwidth. Such memories, which have multiple ports as external terminals, to which the external component units can gain access chronologically parallel, are generally known as multi-port memories. An especially important peripheral condition for economical reasons is naturally the least possible expenditure for surface area on the chip. Other peripheral conditions are due to the demand for the shortest possible access times to the memory cells or ports, and the least possible power loss of the entire memory system.
In the networking area, line cards in today's communications systems are increasingly being challenged on all performance fronts. On one hand, the exponential increase in line rates from OC-12 to OC-48, and now OC-192, has forced designers to greatly increase the throughput requirements of line cards to process at ‘wire speed’. On the other hand, the demands on line card functionality have also increased significantly, as each packet received needs to be examined from Layer 2 all the way through Layer 7. Security Processing, Packet Classification, Content-based switching, Traffic Management, and Per-Flow Queuing are all requirements of today's communication routing and switching systems. These bandwidth and functionality requirements put extra strain on the memory elements in the system.
Packet buffering and memory management have become one of the critical design challenges in packet routing/switching systems today. Recent advances in both SRAM and SDRAM memory technology have aimed to break down the line card memory bottleneck. Double Data Rate (DDR) and Quad Data Rate (QDR) SRAMs have emerged as standard memory solutions that effectively double the per-pin bit rate by clocking the data on both the positive and negative edges of the clock. On the SDRAM front, Reduced Latency DRAM (RLDRAM) and Fast Cycle RAM (FCRAM) are technologies that specifically aim to remove the long latency associated with SDRAM, thereby making DRAM memory more applicable to the high bandwidth random access read/writes that are required in networking line cards. Both DDR/QDR SRAM and the new SDRAM technologies offer significant bandwidth improvements over previous generations, basically providing ‘just enough’ performance to be used in 10 Gbps line card designs. However, while DDR/QDR SRAM and RLDRAM/FCRAM are steps in the right direction in terms of raw bandwidth capability, these are still standard memories that do not specifically address the data-flow needs of typical line cards.
Thus, a multi-ported semiconductor memory having high bandwidth, low latency, and low power, with multiple address and data ports which can easily be reconfigured is desirable.